Drawbacks of the so-called three-transistor (3T) pixel cell or four-transistor (4T) pixel cell of a CMOS imager relate to contact junction leakage, signal loss and contact defects which occur in the contact between a floating diffusion region formed in a substrate and a gate of a source follower output transistor. When a tungsten plug process (which is the current contact metallization of choice) is used to contact the floating diffusion region, tungsten is deposited with tungsten fluoride and a reaction typically takes place between the tungsten fluoride and the substrate. This reaction results in the formation of silicon fluoride which can create worm hole defects in the substrate. These worm holes create, in turn, a conductive channel for current to leak into the substrate. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio of the pixel should be as high as possible. Thus, leakage into the substrate reduces imager performance.
When tungsten is used in contact formation, conventional floating diffusion regions also typically have a n-type doped region (typically a phosphorous- or arsenic-implanted region) to facilitate an ohmic tungsten-semiconductor contact between the contact metallization and the underlying n-doped silicon region to achieve a good charge transfer to the source follower transistor.
Accordingly, resistance in the conductive path between the floating diffusion region and the gate of the source follower transistor should be as low as possible without resulting in added junction leakage. There is needed a new contact technology that provides a low contact resistance to a junction without causing the detrimental leakage mechanisms described above.